Phase lock loops (PLLs) are circuits that generate an output signal whose phase and/or frequency is related to the phase/frequency of an input signal. In some implementations, the input signal may be a reference signal and the PLL adjusts the phase/frequency of its output signal to generally match the phase/frequency of the reference signal.
A PLL takes a finite amount of time to “lock” on to the frequency and phase of the reference signal. Some applications, however, may benefit from, or even require, a relatively short lock time. The Digital Mobil Radio (DMR) standard, for example, may require a PLL to lock within 1.5 ms for a maximum frequency difference of 60 MHz for the output signal. Other standards and applications may have different, yet stringent, specifications for a PLL's lock time.